From 1a522db6f2a5b49e7030fd5deeef1f4d18dfd171 Mon Sep 17 00:00:00 2001
From: Solveig <solvlang@stud.ntnu.no>
Date: Thu, 21 Nov 2024 10:37:38 +0100
Subject: [PATCH] fjernet kode som var kommentert bort
---
controller.vhd | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/controller.vhd b/controller.vhd
index 919f0b0..28079e8 100644
--- a/controller.vhd
+++ b/controller.vhd
@@ -20,8 +20,6 @@ end Controller;
architecture RTL of Controller is
- --signal internal_baud : std_logic_vector(2 downto 0); -- Internt signal for baud
- --signal internal_parity : std_logic_vector(1 downto 0); -- Internt signal for parity
signal turnTaker : std_logic;
signal count : integer;
signal txBusy : std_logic;
@@ -94,17 +92,11 @@ begin
impure function sendDataToTx(databus: std_logic_vector(7 downto 0)) return TxResult is
variable result : TxResult;
begin
- --if txBusy = '0' then
result.adresse_out := "001";
result.data_bus_out := databus;
result.wr_sig_out := '1';
result.rd_sig_out := '0';
- --else
- -- result.adresse_out := "ZZZ";
- -- result.data_bus_out := databus;
- -- result.wr_sig_out := '0';
- -- result.rd_sig_out := '0';
- --end if;
+
return result;
end function sendDataToTx;
@@ -130,7 +122,6 @@ begin
LED_msg <= '0';
Rd_sig <= '0';
txBusy <= '0';
- --Data_bus <= internal_z & parity_out & baud_out;
Wr_sig <= '0';
adresse <= "000";
elsif rising_edge(clk) then
--
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