From 2ecf40199a1bf03eb0dd75efa61254dbb8479e4b Mon Sep 17 00:00:00 2001
From: Nils <nils.e.g.bakken@ntnu.no>
Date: Thu, 7 Nov 2024 19:21:44 +0100
Subject: [PATCH] endret baud_clk til puls

---
 Tx.vhd | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Tx.vhd b/Tx.vhd
index f75d602..fdd4c50 100644
--- a/Tx.vhd
+++ b/Tx.vhd
@@ -125,8 +125,7 @@ begin
 					when others => null;
 				end case;
 
-				-- WIP skal sende når den får write av controller
-				if (baud_clk = '1' and last_baud_clk = '0') or (baud_clk = '0' and last_baud_clk = '1') then
+				if (baud_clk = '1' and last_baud_clk = '0') then
 				case tx_state is
 					when IDLE =>
 						TxD <= '1'; --UART er høy singal når det ikke sendes noe
@@ -164,9 +163,10 @@ begin
 				baud_clk <= '0';
 			elsif rising_edge(clk) then
 				if baud_count = division_factor(baud_rate) - 1 then
-					baud_clk <= not baud_clk;
+					baud_clk <= '1';
 					baud_count <= 0;
 				else
+					baud_clk <= '0';
 					baud_count <= baud_count + 1;
 				end if;
 			end if;
-- 
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