From 3a95b0cdf275a51707ee19d72c92ed008bb31aa6 Mon Sep 17 00:00:00 2001
From: Solveig <solvlang@stud.ntnu.no>
Date: Thu, 14 Nov 2024 15:01:54 +0100
Subject: [PATCH] ferskeste endringene
---
controller.vhd | 32 ++++++++++++++++----------------
controller_tb.vhd | 6 +++---
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/controller.vhd b/controller.vhd
index b8c45c2..f6c66ea 100644
--- a/controller.vhd
+++ b/controller.vhd
@@ -28,7 +28,7 @@ architecture RTL of Controller is
signal internal_z : std_logic_vector(2 downto 0);
signal txBusy : std_logic;
- function resetLogic(count: integer) return integer is
+ procedure resetLogic(inten: integer) is
begin
case Baud_rate_sel is
when "000" => internal_baud(2 downto 0) <= "000";
@@ -48,33 +48,33 @@ architecture RTL of Controller is
end case;
- end function resetLogic;
+ end procedure resetLogic;
- function statusCheck(turnTaker: std_logic)return std_logic is
+ impure function statusCheck(turntaker: std_logic)return std_logic is
begin
if turnTaker = '0' then -- til TX
- Rd_sig <= "1";
+ Rd_sig <= '1';
adresse <= "010";
- turnTaker <= '1';
- return 1;
+ turntaker <= '1';
+ return '1';
else -- Til RX
- Rd_sig <= "1";
+ Rd_sig <= '1';
adresse <= "110";
- turnTaker <= '0';
- return 0;
+ turntaker <= '0';
+ return '0';
end if;
end function statusCheck;
- function getStatusFromRx(databus: std_logic_vector(7 downto 0))return std_logic is
+ impure function getStatusFromRx(databus: std_logic_vector(7 downto 0))return std_logic is
begin
Rd_sig <= '1';
- adress <= "101";
+ adresse <= "101";
end function getStatusFromRx;
- function sendDataToTx(databus: std_logic_vector(7 downto 0)) return std_logic is
+ impure function sendDataToTx(databus: std_logic_vector(7 downto 0)) return std_logic is
begin
if txBusy = '0' then
- adress <= "001";
+ adresse <= "001";
Data_bus <= databus;
Wr_sig <= '1';
else
@@ -95,7 +95,7 @@ begin
-- Reset er starten av oppdraget. Her sendes config-informasjon.
if rst_n = '0' then
- resetLogic(count);
+ resetLogic;
internal_z(2 downto 0) <= "000";
count := 1;
@@ -107,7 +107,7 @@ begin
internal_z(2 downto 0) <= "000";
Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud;
adresse <= "000";
- Wr_sig <= "1";
+ Wr_sig <= '1';
count := count + 1;
elsif count = "2" then
internal_z(2 downto 0) <= "110";
@@ -121,7 +121,7 @@ begin
Data_bus <= "ZZZZZZZZ";
end if;
- statusChecker(turnTaker);
+ turnTaker <= statusChecker(turnTaker);
if Data_bus = "ZZZZZZZZ" then
Rd_sig <= '0';
else if Rd_sig = '1' then
diff --git a/controller_tb.vhd b/controller_tb.vhd
index 2a13196..e646eba 100644
--- a/controller_tb.vhd
+++ b/controller_tb.vhd
@@ -21,7 +21,7 @@ architecture SimulationModel of controller_tb is
LED_msg: out std_logic;
Data_bus : inout std_logic_vector(7 downto 0);
parity_sel: in std_logic_vector(1 downto 0);
- adresse: inout std_logic_vector(2 downto 0);
+ adresse: out std_logic_vector(2 downto 0);
Rd_sig, Wr_sig: out std_logic
);
end component;
@@ -96,7 +96,7 @@ begin
begin
msg_key <= '1';
wait for CLK_PERIOD;
- wait for CLK_PERIOD;
+ --wait for CLK_PERIOD;
msg_key <= '0';
wait for CLK_PERIOD;
end pressButton;
@@ -105,7 +105,7 @@ begin
procedure loopAscii is
begin
wait for 100 ns;
- adresse(2 downto 0) <= "101";
+ adresse <= "101";
--wait until rising_edge(clk);
Data_bus <= "01000001";
--wait until rising_edge(clk);
--
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