diff --git a/Rx.vhd b/Rx.vhd
index 27e59cf063f209adfba66e8cb2e92c7b33d5ef8e..8e4a1dcc83d3f401b8b69a1d3d304ae8bab095fc 100644
--- a/Rx.vhd
+++ b/Rx.vhd
@@ -164,16 +164,16 @@ begin
     --------------------------------------------------------------------------------------------------------------------------------
     --component fifo
     --------------------------------------------------------------------------------------------------------------------------------
-    fifo: entity work.fifo is
+    fifo: entity work.fifo 
         Port map(
-            clock => clk;
-            data => fifo_inn;
-            empty => fifotom;
-            full => fifofull;
-            q => fifo_ut;
-            sclr => fifo_rst;
-            rdreq => fifo_rd_req;
-            wrreq => fifo_wr_req;
+            clock => clk,
+            data => fifo_inn,
+            empty => fifotom,
+            full => fifofull,
+            q => fifo_ut,
+            sclr => fifo_rst,
+            rdreq => fifo_rd_req,
+            wrreq => fifo_wr_req
         );
 
     -------------------------------------------------------------------------------------------------------------------------------