From 79f61b487e0ebc899d621196e060b798b2b63dd1 Mon Sep 17 00:00:00 2001
From: Solveig <solvlang@stud.ntnu.no>
Date: Fri, 15 Nov 2024 17:23:36 +0100
Subject: [PATCH] reset funker. konfig funker
---
controller.vhd | 67 +++++++++++++++++++++++++-------------------------
1 file changed, 34 insertions(+), 33 deletions(-)
diff --git a/controller.vhd b/controller.vhd
index 37e88da..96c93ef 100644
--- a/controller.vhd
+++ b/controller.vhd
@@ -20,10 +20,10 @@ end Controller;
architecture RTL of Controller is
- signal internal_baud : std_logic_vector(2 downto 0); -- Internt signal for baud
- signal internal_parity : std_logic_vector(1 downto 0); -- Internt signal for parity
+ --signal internal_baud : std_logic_vector(2 downto 0); -- Internt signal for baud
+ --signal internal_parity : std_logic_vector(1 downto 0); -- Internt signal for parity
signal turnTaker : std_logic;
- signal internal_z : std_logic_vector(2 downto 0);
+ signal count : integer;
signal txBusy : std_logic;
type StatusResult is record
rd_sig_out : std_logic;
@@ -37,28 +37,30 @@ architecture RTL of Controller is
rd_sig_out : std_logic;
end record;
- procedure resetLogic(
- signal baud_out : out std_logic_vector(2 downto 0);
- signal parity_out : out std_logic_vector(1 downto 0)
- ) is
+ function resetLogic(Baud_rate_sel: std_logic_vector; parity_sel: std_logic_vector)return std_logic_vector is
+ variable baud_out : std_logic_vector(2 downto 0);
+ variable parity_out : std_logic_vector(1 downto 0);
+ variable backbus : std_logic_vector(7 downto 0);
begin
case Baud_rate_sel is
- when "000" => baud_out <= "000";
- when "001" => baud_out <= "001";
- when "010" => baud_out <= "010";
- when "011" => baud_out <= "011";
- when "100" => baud_out <= "100";
- when others => baud_out <= "111";
+ when "000" => baud_out := "000";
+ when "001" => baud_out := "001";
+ when "010" => baud_out := "010";
+ when "011" => baud_out := "011";
+ when "100" => baud_out := "100";
+ when others => baud_out := "111";
end case;
case parity_sel is
- when "00" => parity_out <= "00";
- when "01" => parity_out <= "01";
- when "10" => parity_out <= "10";
- when "11" => parity_out <= "11";
- when others => parity_out <= "00";
+ when "00" => parity_out := "00";
+ when "01" => parity_out := "01";
+ when "10" => parity_out := "10";
+ when "11" => parity_out := "11";
+ when others => parity_out := "00";
end case;
-end procedure;
+ backbus := "ZZZ" & parity_out & baud_out;
+ return backbus;
+end function resetLogic;
function statusCheck(turn_taker: std_logic) return StatusResult is
variable result : StatusResult;
@@ -110,36 +112,35 @@ begin
p_clk : process(clk, rst_n)
variable internal_data : std_logic_vector(7 downto 0);
- variable count : integer := 1;
variable status_result : StatusResult;
variable tx_result : TxResult;
begin
-- Reset er starten av oppdraget. Her sendes config-informasjon.
if rst_n = '0' then
- resetLogic(internal_baud, internal_parity);
- internal_z <= "000";
- count := 1;
+ Data_bus <= "ZZZZZZZZ";
+ count <= 1;
turnTaker <= '0';
LED_msg <= '0';
+ Rd_sig <= '0';
txBusy <= '0';
- Data_bus <= internal_z & internal_parity & internal_baud;
- Wr_sig <= '1';
+ --Data_bus <= internal_z & parity_out & baud_out;
+ Wr_sig <= '0';
adresse <= "000";
elsif rising_edge(clk) then
if count = 1 then
- internal_z(2 downto 0) <= "000";
- Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud;
+ -- Sender konfigurasjon til TX konfig
+ Data_bus <= resetLogic(Baud_rate_sel, parity_sel);
adresse <= "000";
Wr_sig <= '1';
- count := count + 1;
+ count <= count + 1;
elsif count = 2 then
- internal_z(2 downto 0) <= "110";
- Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud;
- adresse <= "110";
+ -- Sender konfigurasjon til RX konfig
+ Data_bus <= resetLogic(Baud_rate_sel, parity_sel);
+ adresse <= "100";
Wr_sig <= '1';
- count := count + 1;
+ count <= count + 1;
else
Wr_sig <= '0';
Rd_sig <= '0';
@@ -151,7 +152,7 @@ begin
Wr_sig <= '1';
adresse <= "001";
- else
+ elsif count = 3 then
status_result := statusCheck(turnTaker);
Rd_sig <= status_result.rd_sig_out;
--
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