diff --git a/controller_tb.vhd b/controller_tb.vhd
index 1b69157fbc0cf0893a8df199e9c20bf4c39a0aa1..5549a48322c22aeb7453852f938721006609d3ad 100644
--- a/controller_tb.vhd
+++ b/controller_tb.vhd
@@ -13,7 +13,7 @@ architecture SimulationModel of controller_tb is
     -- Constant declaration
     constant CLK_PERIOD : time := 20 ns;  -- 50 MHz klokke
 	
-    -- Component declarasion
+    -- Component declarasion hihi
     component controller
         Port (
             clk, rst_n, msg_key: in std_logic;