diff --git a/controller.vhd b/controller.vhd index 144f46a13b03dc23e8e32eb2c3e6eef1e283cd31..bbbdd1ab62200bc1b004180fd421f64fea5a6afc 100644 --- a/controller.vhd +++ b/controller.vhd @@ -20,25 +20,16 @@ end Controller; architecture RTL of Controller is -type reader_status is (reading, idle); - signal status : reader_status := idle; signal internal_baud : std_logic_vector(2 downto 0); -- Internal signal for baud signal internal_parity : std_logic_vector(1 downto 0); -- Internt signal for parity + variable internal_data : std_logic_vector(7 downto 0); -- Intern databus data + variable count : integer; + signal turnTaker : std_logic; signal internal_z : std_logic_vector(2 downto 0); - - --Arkitekturen begynner -begin - - -- Rd_sig <= '1' when status = reading else '0'; --- prosessen begynner - - p_clk : process(clk, rst_n, msg_key, Baud_rate_sel, parity_sel, Data_bus) - begin - - -- Reset er starten av oppdraget. Her sendes config-informasjon. - if rst_n = '0' then - case Baud_rate_sel is + function resetLogic(count: integer) return integer is + begin + case Baud_rate_sel is when "000" => internal_baud(2 downto 0) <= "000"; when "001" => internal_baud(2 downto 0) <= "001"; when "010" => internal_baud(2 downto 0) <= "010"; @@ -54,43 +45,66 @@ begin when "11" => internal_parity(1 downto 0) <= "11"; when others => internal_parity(1 downto 0) <= "00"; -- Default end case; + + + end function resetLogic; + + function statusCheck(turnTaker: std_logic)return std_logic is + begin + if turnTaker = '0' then -- til TX + Rd_sig <= "1"; + adresse <= "010"; + turnTaker <= '1'; + return 1; + else + Rd_sig <= "1"; + adresse <= "110"; + turnTaker <= '0'; + return 0; + end if; + end function statusCheck; + + + --Arkitekturen begynner +begin + +-- prosessen begynner + + p_clk : process(all) + begin + + -- Reset er starten av oppdraget. Her sendes config-informasjon. + if rst_n = '0' then + resetLogic(count); internal_z(2 downto 0) <= "000"; - + count := 1; Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud; Wr_sig <= '1'; adresse <= "000"; elsif rising_edge(clk) then - --status <= idle; - --Wr_sig <= '0'; - - -- Hvis meldingsknappen trykkes, da sender vi en pre-definert bokstav til TX for videresending. - if msg_key = '1' then - Data_bus <= "01000101"; - Wr_sig <= '1'; - adresse <= "001"; - - else - - --Hvis RX har mottatt noe data, så skal vi sende videre. Vi skal også skru på led-paeren. - - if adresse = "101" then - status <= reading; - LED_msg <= '1'; - adresse <= "001"; - Wr_sig <= '1'; - --status <= idle; - - else - Data_bus <= "ZZZZZZZZ"; - adresse <= "ZZZ"; - Wr_sig <= '0'; - Rd_sig <= '0'; - --status <= idle; - end if; - end if; - end if; - --end if; + if count = "1" then + internal_z(2 downto 0) <= "000"; + Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud; + adresse <= "000"; + Wr_sig <= "1"; + count := count + 1; + elsif count = "2" then + internal_z(2 downto 0) <= "110"; + Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud; + adresse <= "110"; + Wr_sig <= "1"; + count := count + 1; + else + Wr_sig <= "0"; + Data_bus <= "ZZZZZZZZ"; + end if; + + statusChecker(turnTaker); + + end if; + + end process p_clk; end RTL; diff --git a/controller_tb.vhd b/controller_tb.vhd index b3261459d7fa64a8624469ac423c41339973388d..2a131966e28d551386e11832f0e34a42a98dd935 100644 --- a/controller_tb.vhd +++ b/controller_tb.vhd @@ -21,7 +21,7 @@ architecture SimulationModel of controller_tb is LED_msg: out std_logic; Data_bus : inout std_logic_vector(7 downto 0); parity_sel: in std_logic_vector(1 downto 0); - adresse: out std_logic_vector(2 downto 0); + adresse: inout std_logic_vector(2 downto 0); Rd_sig, Wr_sig: out std_logic ); end component; @@ -50,8 +50,9 @@ begin msg_key => msg_key, Baud_rate_sel => Baud_rate_sel, parity_sel => parity_sel, - Rd_sig => Rd_sig, - Wr_sig => Wr_sig + LED_msg => LED_msg, + Rd_sig => Rd_sig, + Wr_sig => Wr_sig ); -- Generation of clock @@ -84,6 +85,7 @@ begin Data_bus <= "ZZZZZZZZ"; Wr_sig <= 'Z'; Rd_sig <= 'Z'; + LED_msg <= '0'; wait until rst_n = '1'; wait for 100 ns; wait until rising_edge(clk); @@ -97,11 +99,6 @@ begin wait for CLK_PERIOD; msg_key <= '0'; wait for CLK_PERIOD; - - --if Data_bus(7 downto 0) = "01000001" then - --assert True; - --else assert false; - -- end if; end pressButton; @@ -109,7 +106,7 @@ begin begin wait for 100 ns; adresse(2 downto 0) <= "101"; - wait until rising_edge(clk); + --wait until rising_edge(clk); Data_bus <= "01000001"; --wait until rising_edge(clk); --assert Rd_sig = '1';