From 9acae595d9965dcbb20e5bee8be85f5a9d9f29b0 Mon Sep 17 00:00:00 2001 From: Solveig <solvlang@stud.ntnu.no> Date: Fri, 15 Nov 2024 20:46:37 +0100 Subject: [PATCH] =?UTF-8?q?veldig=20MVP=20p=C3=A5=20controller?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- controller.vhd | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/controller.vhd b/controller.vhd index b28c77f..f3fa907 100644 --- a/controller.vhd +++ b/controller.vhd @@ -28,6 +28,7 @@ architecture RTL of Controller is signal rxIncomingData: std_logic; type StatusResult is record rd_sig_out : std_logic; + wr_sig_out : std_logic; adresse_out : std_logic_vector(2 downto 0); turn_taker_out : std_logic; end record; @@ -69,10 +70,12 @@ begin if turn_taker = '0' then result.rd_sig_out := '1'; result.adresse_out := "010"; + result.wr_sig_out := '0'; result.turn_taker_out := '1'; elsif turn_taker = '1' then result.rd_sig_out := '1'; result.adresse_out := "110"; + result.wr_sig_out := '0'; result.turn_taker_out := '0'; end if; @@ -92,17 +95,15 @@ begin variable result : TxResult; begin if txBusy = '0' then - if databus() result.adresse_out := "001"; result.data_bus_out := databus; - result.wr_sig_out := '0'; - result.rd_sig_out := '1'; - end if; + result.wr_sig_out := '1'; + result.rd_sig_out := '0'; else result.adresse_out := "ZZZ"; result.data_bus_out := databus; result.wr_sig_out := '0'; - result.rd_sig_out := '1'; + result.rd_sig_out := '0'; end if; return result; end function sendDataToTx; @@ -133,6 +134,7 @@ begin Wr_sig <= '0'; adresse <= "000"; elsif rising_edge(clk) then + Data_bus <= "ZZZZZZZZ"; if count = 1 then -- Sender konfigurasjon til TX konfig Data_bus <= resetLogic(Baud_rate_sel, parity_sel); @@ -153,10 +155,19 @@ begin Rd_sig <= '0'; adresse <= "001"; + else if rxIncomingData = '1' and txBusy = '0' then + + tx_result := sendDataToTx(Data_bus); + adresse <= tx_result.adresse_out; + Data_bus <= tx_result.data_bus_out; + Wr_sig <= tx_result.wr_sig_out; + Rd_sig <= '0'; + rxIncomingData <= '0'; else -- normal klokkelogikk. Annahver polling av RX og TX for status. status_result := statusCheck(turnTaker); Rd_sig <= status_result.rd_sig_out; + Wr_sig <= status_result.wr_sig_out; adresse <= status_result.adresse_out; turnTaker <= status_result.turn_taker_out; if turnTaker = '1' then -- da skal vi sjekke om TX er busy @@ -165,18 +176,11 @@ begin Data_bus <= "ZZZZZZZZ"; elsif Data_bus(0 downto 0) = "0" then txBusy <= '0'; + + end if; elsif turnTaker = '0' then -- Skal sjekke om Rx har data til oss, status på fifo osv. - status_result := getStatusFromRx(Data_bus); - Rd_sig <= status_result.rd_sig_out; - adresse <= status_result.adresse_out; - turnTaker <= status_result.turn_taker_out; - if txBusy = '0' then - tx_result := sendDataToTx(Data_bus); - adresse <= tx_result.adresse_out; - Data_bus <= tx_result.data_bus_out; - Wr_sig <= tx_result.wr_sig_out; - Rd_sig <= '0'; + rxIncomingData <= '1'; else --do nothing end if; @@ -185,8 +189,6 @@ begin end if; end if; end if; - - end process p_clk; -- GitLab