diff --git a/Rx.vhd b/Rx.vhd
index 1e6c9a6ab98118f52f38b084ae0fa6ce03ff5334..32c668c926d2180aea13170ea725e1329492a581 100644
--- a/Rx.vhd
+++ b/Rx.vhd
@@ -1,8 +1,8 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-library Files;
-use Files.fifo;
+library work;
+use work.fifo;
entity Rx is
generic(
@@ -30,7 +30,7 @@ architecture Behavioral of Rx is
type paritets_sjekk is (ingen, partall, oddetall);
type baud_speed is (B115k,B576,B384,B192,B096);
--------------------------------------------------------------------------------------------------------------------------------
- --Signaler
+ --Sigwork
--------------------------------------------------------------------------------------------------------------------------------
signal datalest: std_logic_vector(10 downto 0):="11111111111";
signal datasamplet: std_logic_vector(7 downto 0):="00000000";
@@ -167,7 +167,7 @@ begin
--------------------------------------------------------------------------------------------------------------------------------
--component fifo
--------------------------------------------------------------------------------------------------------------------------------
- fifo: entity Files.fifo
+ fifo: entity work.fifo
Port map(
clock => clk,
data => fifo_inn,
@@ -210,35 +210,40 @@ begin
--en startbit, før den bruker parity_checker funksjonen mtp hvilken paritetssjekk man har. Hvis parity-checker returnerer true
--sendes dataen inn i fifoen, hvis ikke så forkastes den.
-------------------------------------------------------------------------------------------------------------------------------
- databehandling: process(clk,rst_n) is
- begin
- if rst_n = '0' then
-
- elsif rising_edge(clk) and datalest(10) = '0' then
- if parity_checker(parity_check,datalest) = true then
- fifo_wr_req <= '1';
+databehandling: process(clk, rst_n)
+begin
+ if rst_n = '0' then
+ datalest(10 downto 0) <= (others => '0');
+ fifo_wr_req <= '0'; -- Nullstille fifo_wr_req under reset
+ paritetsfeil <= '0'; -- Nullstille paritetsfeil under reset
+ elsif rising_edge(clk) then
+ if datalest(10) = '0' then
+ if parity_checker(parity_check, datalest) = true then
+ fifo_wr_req <= '1'; -- Aktiver fifo_wr_req når paritetskontroll er gyldig
case parity_check is
when ingen =>
fifo_inn <= datalest(9 downto 2);
datalest(10 downto 1) <= (others => '1');
- when others =>
+ when others =>
fifo_inn <= datalest(9 downto 2);
datalest(10 downto 0) <= (others => '1');
end case;
+ paritetsfeil <= '0'; -- Nullstill paritetsfeil
else
- datalest <= (others => '1'); -- Kontrollsjekk denne før innsending
+ datalest <= (others => '1'); -- Feilhåndtering
paritetsfeil <= '1';
+ fifo_wr_req <= '0'; -- Deaktiver fifo_wr_req ved feil
end if;
else
- fifo_wr_req <= '0';
- --sette inn logikk
+ fifo_wr_req <= '0'; -- Deaktiver fifo_wr_req hvis datalest(10) ikke er '0'
end if;
+ end if;
+end process;
- end process;
kommunikasjon: process(clk, rst_n) is
begin
- fifo_rd_req <= '0';
if rst_n = '0' then
+ fifo_rd_req <= '0';
elsif rising_edge(clk) then
case adresse is
when "100" =>
diff --git a/Rx_tb.vhd b/Rx_tb.vhd
index 737767ed5ef07ccc7e11559b8313027ff32fa1f9..b6046586774572f31d5052e01ff79986c0dd4af9 100644
--- a/Rx_tb.vhd
+++ b/Rx_tb.vhd
@@ -7,7 +7,7 @@ entity Rx_tb is
end Rx_tb;
architecture Behavioral of Rx_tb is
-
+ constant clk_T : time := 20 ns;
-- Testbenkens signaler
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
@@ -40,7 +40,7 @@ architecture Behavioral of Rx_tb is
begin
-- Instansiering av Rx-enheten
- uut: Rx
+ uut:component Rx
port map (
clk => clk,
rst_n => rst_n,
@@ -54,12 +54,10 @@ begin
-- Klokkeprosessen genererer et 50 MHz klokkesignal
clk_process: process
begin
- while true loop
- clk <= '0';
- wait for 10 ns;
- clk <= '1';
- wait for 10 ns;
- end loop;
+ clk <= '0';
+ wait for clk_T/2;
+ clk <= '1';
+ wait for clk_T/2;
end process;
-- Stimuli for reset og testoperasjoner
@@ -92,9 +90,10 @@ begin
wait for 20 ns;
Wr_sig <= '0';
+
-- Flere tester kan settes opp her
-- Slutt på simuleringen
- wait;
+ assert false report "TB ferdig" severity failure;
end process;
end Behavioral;
diff --git a/controller.vhd b/controller.vhd
index 144f46a13b03dc23e8e32eb2c3e6eef1e283cd31..bbbdd1ab62200bc1b004180fd421f64fea5a6afc 100644
--- a/controller.vhd
+++ b/controller.vhd
@@ -20,25 +20,16 @@ end Controller;
architecture RTL of Controller is
-type reader_status is (reading, idle);
- signal status : reader_status := idle;
signal internal_baud : std_logic_vector(2 downto 0); -- Internal signal for baud
signal internal_parity : std_logic_vector(1 downto 0); -- Internt signal for parity
+ variable internal_data : std_logic_vector(7 downto 0); -- Intern databus data
+ variable count : integer;
+ signal turnTaker : std_logic;
signal internal_z : std_logic_vector(2 downto 0);
-
- --Arkitekturen begynner
-begin
-
- -- Rd_sig <= '1' when status = reading else '0';
--- prosessen begynner
-
- p_clk : process(clk, rst_n, msg_key, Baud_rate_sel, parity_sel, Data_bus)
- begin
-
- -- Reset er starten av oppdraget. Her sendes config-informasjon.
- if rst_n = '0' then
- case Baud_rate_sel is
+ function resetLogic(count: integer) return integer is
+ begin
+ case Baud_rate_sel is
when "000" => internal_baud(2 downto 0) <= "000";
when "001" => internal_baud(2 downto 0) <= "001";
when "010" => internal_baud(2 downto 0) <= "010";
@@ -54,43 +45,66 @@ begin
when "11" => internal_parity(1 downto 0) <= "11";
when others => internal_parity(1 downto 0) <= "00"; -- Default
end case;
+
+
+ end function resetLogic;
+
+ function statusCheck(turnTaker: std_logic)return std_logic is
+ begin
+ if turnTaker = '0' then -- til TX
+ Rd_sig <= "1";
+ adresse <= "010";
+ turnTaker <= '1';
+ return 1;
+ else
+ Rd_sig <= "1";
+ adresse <= "110";
+ turnTaker <= '0';
+ return 0;
+ end if;
+ end function statusCheck;
+
+
+ --Arkitekturen begynner
+begin
+
+-- prosessen begynner
+
+ p_clk : process(all)
+ begin
+
+ -- Reset er starten av oppdraget. Her sendes config-informasjon.
+ if rst_n = '0' then
+ resetLogic(count);
internal_z(2 downto 0) <= "000";
-
+ count := 1;
Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud;
Wr_sig <= '1';
adresse <= "000";
elsif rising_edge(clk) then
- --status <= idle;
- --Wr_sig <= '0';
-
- -- Hvis meldingsknappen trykkes, da sender vi en pre-definert bokstav til TX for videresending.
- if msg_key = '1' then
- Data_bus <= "01000101";
- Wr_sig <= '1';
- adresse <= "001";
-
- else
-
- --Hvis RX har mottatt noe data, så skal vi sende videre. Vi skal også skru på led-paeren.
-
- if adresse = "101" then
- status <= reading;
- LED_msg <= '1';
- adresse <= "001";
- Wr_sig <= '1';
- --status <= idle;
-
- else
- Data_bus <= "ZZZZZZZZ";
- adresse <= "ZZZ";
- Wr_sig <= '0';
- Rd_sig <= '0';
- --status <= idle;
- end if;
- end if;
- end if;
- --end if;
+ if count = "1" then
+ internal_z(2 downto 0) <= "000";
+ Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud;
+ adresse <= "000";
+ Wr_sig <= "1";
+ count := count + 1;
+ elsif count = "2" then
+ internal_z(2 downto 0) <= "110";
+ Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud;
+ adresse <= "110";
+ Wr_sig <= "1";
+ count := count + 1;
+ else
+ Wr_sig <= "0";
+ Data_bus <= "ZZZZZZZZ";
+ end if;
+
+ statusChecker(turnTaker);
+
+ end if;
+
+
end process p_clk;
end RTL;
diff --git a/controller_tb.vhd b/controller_tb.vhd
index b3261459d7fa64a8624469ac423c41339973388d..2a131966e28d551386e11832f0e34a42a98dd935 100644
--- a/controller_tb.vhd
+++ b/controller_tb.vhd
@@ -21,7 +21,7 @@ architecture SimulationModel of controller_tb is
LED_msg: out std_logic;
Data_bus : inout std_logic_vector(7 downto 0);
parity_sel: in std_logic_vector(1 downto 0);
- adresse: out std_logic_vector(2 downto 0);
+ adresse: inout std_logic_vector(2 downto 0);
Rd_sig, Wr_sig: out std_logic
);
end component;
@@ -50,8 +50,9 @@ begin
msg_key => msg_key,
Baud_rate_sel => Baud_rate_sel,
parity_sel => parity_sel,
- Rd_sig => Rd_sig,
- Wr_sig => Wr_sig
+ LED_msg => LED_msg,
+ Rd_sig => Rd_sig,
+ Wr_sig => Wr_sig
);
-- Generation of clock
@@ -84,6 +85,7 @@ begin
Data_bus <= "ZZZZZZZZ";
Wr_sig <= 'Z';
Rd_sig <= 'Z';
+ LED_msg <= '0';
wait until rst_n = '1';
wait for 100 ns;
wait until rising_edge(clk);
@@ -97,11 +99,6 @@ begin
wait for CLK_PERIOD;
msg_key <= '0';
wait for CLK_PERIOD;
-
- --if Data_bus(7 downto 0) = "01000001" then
- --assert True;
- --else assert false;
- -- end if;
end pressButton;
@@ -109,7 +106,7 @@ begin
begin
wait for 100 ns;
adresse(2 downto 0) <= "101";
- wait until rising_edge(clk);
+ --wait until rising_edge(clk);
Data_bus <= "01000001";
--wait until rising_edge(clk);
--assert Rd_sig = '1';
diff --git a/modelsim.ini b/modelsim.ini
new file mode 100644
index 0000000000000000000000000000000000000000..ffc6cc4961fd3fa15e228d7b44dc16e161c73ff7
--- /dev/null
+++ b/modelsim.ini
@@ -0,0 +1,361 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+others = C:/intelFPGA/20.1/modelsim_ase/win32aloem/../modelsim.ini
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+;
+; Verilog Section
+;
+
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2008
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+NoDebug = 0
+CheckSynthesis = 0
+NoVitalCheck = 0
+Optimize_1164 = 1
+NoVital = 0
+Quiet = 0
+Show_source = 0
+DisableOpt = 0
+ZeroIn = 0
+CoverageNoSub = 0
+NoCoverage = 1
+CoverCells = 0
+CoverExcludeDefault = 0
+CoverFEC = 1
+CoverShortCircuit = 1
+CoverOpt = 3
+Show_Warning1 = 1
+Show_Warning2 = 1
+Show_Warning3 = 1
+Show_Warning4 = 1
+Show_Warning5 = 1
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+vlog95compat = 0
+Vlog01Compat = 0
+Svlog = 0
+CoverCells = 0
+CoverExcludeDefault = 0
+CoverFEC = 1
+CoverShortCircuit = 1
+CoverOpt = 3
+OptionFile = C:/Users/debno/OneDrive/Dokumenter/skole/NTNU/IELEG2213 Programerbare kretser/bigSysytem/progkrets/vlog.opt
+Quiet = 0
+Show_source = 0
+NoDebug = 0
+Hazard = 0
+UpCase = 0
+DisableOpt = 0
+ZeroIn = 0
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license isn't available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type). Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+VoptFlow = 1
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer). The other settings
+; are to send messages only to the transcript or only to the
+; wlf file. The valid values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
diff --git a/vlog.opt b/vlog.opt
new file mode 100644
index 0000000000000000000000000000000000000000..139597f9cb07c5d48bed18984ec4747f4b4f3438
--- /dev/null
+++ b/vlog.opt
@@ -0,0 +1,2 @@
+
+
diff --git a/vsim.wlf b/vsim.wlf
new file mode 100644
index 0000000000000000000000000000000000000000..f8135986d2cf686551360b6adbad6c6e0573d1d2
Binary files /dev/null and b/vsim.wlf differ
diff --git a/work/_info b/work/_info
new file mode 100644
index 0000000000000000000000000000000000000000..73702cca3075fdf4adfd6e6b96ba0f37a4c589f3
--- /dev/null
+++ b/work/_info
@@ -0,0 +1,140 @@
+m255
+K4
+z2
+!s11e vcom 2020.1 2020.02, Feb 28 2020
+13
+!s112 1.1
+!i10d 8192
+!i10e 25
+!i10f 100
+cModel Technology
+Z0 dC:/Users/debno/OneDrive/Dokumenter/skole/NTNU/IELEG2213 Programerbare kretser/bigSysytem/progkrets
+Efifo
+Z1 w1730990335
+Z2 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
+Z3 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
+!i122 6
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