Tx_tb.vhd

-- Testbench of Tx
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Entity of testbench (empty)
entity Tx_tb is
end Tx_tb;

architecture SimulationModel of Tx_tb is

    -- Constant declaration
    constant CLK_PERIOD : time := 20 ns;  -- 50 MHz klokke
	
    -- Component declarasion
    component Tx
        Port (
            clk         : in  std_logic;
            rst_n       : in  std_logic;
	    Rd_sig      : in std_logic;
	    Wr_sig      : in std_logic;
            adresse     : in std_logic_vector(2 downto 0);
            Data_bus    : inout std_logic_vector(7 downto 0);
            TxD         : out std_logic
        );
    end component;

    -- Signal declaration
    signal clk      : std_logic := '0';
    signal rst_n    : std_logic := '1';
    signal adresse  : std_logic_vector(2 downto 0);
    signal Data_bus : std_logic_vector(7 downto 0);
    signal TxD      : std_logic;
    signal Rd_sig   : std_logic;
    signal Wr_sig   : std_logic;

begin

    -- Component instantiations UART TX-modul (DUT)
    DUT: component Tx
        Port Map (
            clk         => clk,
            rst_n       => rst_n,
            adresse     => adresse,
            Data_bus    => Data_bus,
            TxD         => TxD,
	    Rd_sig      => Rd_sig,
	    Wr_sig	=> Wr_sig
        );

    -- Generation of clock
    p_clk: process is
    begin
        clk <= '0';
        wait for CLK_PERIOD / 2;
        clk <= '1';
        wait for CLK_PERIOD / 2;
    end process;

    --Generation of resetN
    p_rst_n: process is
    begin
      rst_n <= '0';
      wait for 2.2*CLK_PERIOD;
      rst_n <= '1';
      wait;
    end process;

    -- Test procedure
    p_test_procedure: process