kompilerende versjon. Uferdig

controller.vhd

@@ -26,6 +26,7 @@ architecture RTL of Controller is
 	 variable count : integer;
 	 signal turnTaker : std_logic;
 	 signal internal_z : std_logic_vector(2 downto 0);
+	 signal txBusy : std_logic;
 	 
 	 function resetLogic(count: integer) return integer is
 	 begin 
@@ -56,7 +57,7 @@ architecture RTL of Controller is
 		 adresse <= "010";
 		 turnTaker <= '1';
 		 return 1;
-		 else 
+		 else  -- Til RX
 		 Rd_sig <= "1";
 		 adresse <= "110";
 		 turnTaker <= '0';
@@ -93,16 +94,29 @@ begin
 				 internal_z(2 downto 0) <= "110";
 				 Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud;
 				 adresse <= "110";
-				 Wr_sig <= "1";
+				 Wr_sig <= '1';
 				 count := count + 1;
 				 else 
-				 Wr_sig <= "0";
+				 Wr_sig <= '0';
+				 Rd_sig <= '0';
 				 Data_bus <= "ZZZZZZZZ";
 				 end if;
 				 
 				statusChecker(turnTaker);
+				if Data_bus = "ZZZZZZZZ" then
+					--do nothing
+				else
+					if turnTaker = '1' then -- da skal vi sjekke om TX er busy
+						if Data_bus(0 downto 0) = "1" then 
+							txBusy <= '1';
+					elsif turnTaker = '0' then -- Skal sjekke om Rx har data til oss, status på fifo osv.
+						--if Data_bus()
+					end if;
+					end if;
+					end if;
 		  
 		  end if;
+		  --end if;
 	
 	
     end process p_clk;