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Solveig Langbakk
progkrets
Commits
75c574ff
Commit
75c574ff
authored
7 months ago
by
Solveig Langbakk
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fikser Read-write logikk
parent
79f61b48
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controller.vhd
+33
-32
33 additions, 32 deletions
controller.vhd
with
33 additions
and
32 deletions
controller.vhd
+
33
−
32
View file @
75c574ff
...
@@ -25,6 +25,7 @@ architecture RTL of Controller is
...
@@ -25,6 +25,7 @@ architecture RTL of Controller is
signal
turnTaker
:
std_logic
;
signal
turnTaker
:
std_logic
;
signal
count
:
integer
;
signal
count
:
integer
;
signal
txBusy
:
std_logic
;
signal
txBusy
:
std_logic
;
signal
rxIncomingData
:
std_logic
;
type
StatusResult
is
record
type
StatusResult
is
record
rd_sig_out
:
std_logic
;
rd_sig_out
:
std_logic
;
adresse_out
:
std_logic_vector
(
2
downto
0
);
adresse_out
:
std_logic_vector
(
2
downto
0
);
...
@@ -91,10 +92,12 @@ begin
...
@@ -91,10 +92,12 @@ begin
variable
result
:
TxResult
;
variable
result
:
TxResult
;
begin
begin
if
txBusy
=
'0'
then
if
txBusy
=
'0'
then
if
databus
()
result
.
adresse_out
:
=
"001"
;
result
.
adresse_out
:
=
"001"
;
result
.
data_bus_out
:
=
databus
;
result
.
data_bus_out
:
=
databus
;
result
.
wr_sig_out
:
=
'0'
;
result
.
wr_sig_out
:
=
'0'
;
result
.
rd_sig_out
:
=
'1'
;
result
.
rd_sig_out
:
=
'1'
;
end
if
;
else
else
result
.
adresse_out
:
=
"ZZZ"
;
result
.
adresse_out
:
=
"ZZZ"
;
result
.
data_bus_out
:
=
databus
;
result
.
data_bus_out
:
=
databus
;
...
@@ -122,6 +125,7 @@ begin
...
@@ -122,6 +125,7 @@ begin
Data_bus
<=
"ZZZZZZZZ"
;
Data_bus
<=
"ZZZZZZZZ"
;
count
<=
1
;
count
<=
1
;
turnTaker
<=
'0'
;
turnTaker
<=
'0'
;
rxIncomingData
<=
'0'
;
LED_msg
<=
'0'
;
LED_msg
<=
'0'
;
Rd_sig
<=
'0'
;
Rd_sig
<=
'0'
;
txBusy
<=
'0'
;
txBusy
<=
'0'
;
...
@@ -141,48 +145,45 @@ begin
...
@@ -141,48 +145,45 @@ begin
adresse
<=
"100"
;
adresse
<=
"100"
;
Wr_sig
<=
'1'
;
Wr_sig
<=
'1'
;
count
<=
count
+
1
;
count
<=
count
+
1
;
else
elsif
count
=
3
then
Wr_sig
<=
'0'
;
Rd_sig
<=
'0'
;
Data_bus
<=
"ZZZZZZZZ"
;
end
if
;
if
msg_key
=
'1'
then
if
msg_key
=
'1'
then
Data_bus
<=
"01000101"
;
Data_bus
<=
"01000101"
;
Wr_sig
<=
'1'
;
Wr_sig
<=
'1'
;
Rd_sig
<=
'0'
;
adresse
<=
"001"
;
adresse
<=
"001"
;
els
if
count
=
3
then
els
e
-- normal klokkelogikk. Annahver polling av RX og TX for status.
status_result
:
=
statusCheck
(
turnTaker
);
status_result
:
=
statusCheck
(
turnTaker
);
Rd_sig
<=
status_result
.
rd_sig_out
;
Rd_sig
<=
status_result
.
rd_sig_out
;
adresse
<=
status_result
.
adresse_out
;
adresse
<=
status_result
.
adresse_out
;
turnTaker
<=
status_result
.
turn_taker_out
;
turnTaker
<=
status_result
.
turn_taker_out
;
if
Data_bus
=
"ZZZZZZZZ"
then
Rd_sig
<=
'0'
;
elsif
Rd_sig
=
'1'
then
tx_result
:
=
sendDataToTx
(
Data_bus
);
adresse
<=
tx_result
.
adresse_out
;
Data_bus
<=
tx_result
.
data_bus_out
;
Wr_sig
<=
tx_result
.
wr_sig_out
;
Rd_sig
<=
'0'
;
else
if
turnTaker
=
'1'
then
-- da skal vi sjekke om TX er busy
if
turnTaker
=
'1'
then
-- da skal vi sjekke om TX er busy
if
Data_bus
(
0
downto
0
)
=
"1"
then
if
Data_bus
(
0
downto
0
)
=
"1"
then
txBusy
<=
'1'
;
txBusy
<=
'1'
;
Data_bus
<=
"ZZZZZZZZ"
;
Data_bus
<=
"ZZZZZZZZ"
;
elsif
Data_bus
(
0
downto
0
)
=
"0"
then
txBusy
<=
'0'
;
elsif
turnTaker
=
'0'
then
-- Skal sjekke om Rx har data til oss, status på fifo osv.
elsif
turnTaker
=
'0'
then
-- Skal sjekke om Rx har data til oss, status på fifo osv.
status_result
:
=
getStatusFromRx
(
Data_bus
);
status_result
:
=
getStatusFromRx
(
Data_bus
);
Rd_sig
<=
status_result
.
rd_sig_out
;
Rd_sig
<=
status_result
.
rd_sig_out
;
adresse
<=
status_result
.
adresse_out
;
adresse
<=
status_result
.
adresse_out
;
turnTaker
<=
status_result
.
turn_taker_out
;
turnTaker
<=
status_result
.
turn_taker_out
;
if
txBusy
=
'0'
then
tx_result
:
=
sendDataToTx
(
Data_bus
);
adresse
<=
tx_result
.
adresse_out
;
Data_bus
<=
tx_result
.
data_bus_out
;
Wr_sig
<=
tx_result
.
wr_sig_out
;
Rd_sig
<=
'0'
;
else
else
--do nothing
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
...
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