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Commit 936d45b6 authored by Solveig Langbakk's avatar Solveig Langbakk
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skjellett til noe funksjonalitet oppe

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controller.vhd
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...@@ -20,69 +20,86 @@ end Controller; ...@@ -20,69 +20,86 @@ end Controller;
architecture RTL of Controller is architecture RTL of Controller is
signal internal_baud : std_logic_vector(2 downto 0); -- Internal signal for baud signal internal_baud : std_logic_vector(2 downto 0); -- Internt signal for baud
signal internal_parity : std_logic_vector(1 downto 0); -- Internt signal for parity signal internal_parity : std_logic_vector(1 downto 0); -- Internt signal for parity
variable internal_data : std_logic_vector(7 downto 0); -- Intern databus data
variable count : integer;
signal turnTaker : std_logic; signal turnTaker : std_logic;
signal internal_z : std_logic_vector(2 downto 0); signal internal_z : std_logic_vector(2 downto 0);
signal txBusy : std_logic; signal txBusy : std_logic;
type StatusResult is record
rd_sig_out : std_logic;
adresse_out : std_logic_vector(2 downto 0);
turn_taker_out : std_logic;
end record;
type TxResult is record
adresse_out : std_logic_vector(2 downto 0);
data_bus_out : std_logic_vector(7 downto 0);
wr_sig_out : std_logic;
rd_sig_out : std_logic;
end record;
procedure resetLogic(inten: integer) is procedure resetLogic(
begin signal baud_out : out std_logic_vector(2 downto 0);
case Baud_rate_sel is signal parity_out : out std_logic_vector(1 downto 0)
when "000" => internal_baud(2 downto 0) <= "000"; ) is
when "001" => internal_baud(2 downto 0) <= "001"; begin
when "010" => internal_baud(2 downto 0) <= "010"; case Baud_rate_sel is
when "011" => internal_baud(2 downto 0) <= "011"; when "000" => baud_out <= "000";
when "100" => internal_baud(2 downto 0) <= "100"; when "001" => baud_out <= "001";
when others => internal_baud(2 downto 0) <= "111"; when "010" => baud_out <= "010";
end case; when "011" => baud_out <= "011";
when "100" => baud_out <= "100";
when others => baud_out <= "111";
end case;
case parity_sel is case parity_sel is
when "00" => internal_parity(1 downto 0) <= "00"; when "00" => parity_out <= "00";
when "01" => internal_parity(1 downto 0) <= "01"; when "01" => parity_out <= "01";
when "10" => internal_parity(1 downto 0) <= "10"; when "10" => parity_out <= "10";
when "11" => internal_parity(1 downto 0) <= "11"; when "11" => parity_out <= "11";
when others => internal_parity(1 downto 0) <= "00"; -- Default when others => parity_out <= "00";
end case; end case;
end procedure;
function statusCheck(turn_taker: std_logic) return StatusResult is
variable result : StatusResult;
begin
if turn_taker = '0' then
result.rd_sig_out := '1';
result.adresse_out := "010";
result.turn_taker_out := '1';
else
result.rd_sig_out := '1';
result.adresse_out := "110";
result.turn_taker_out := '0';
end if;
return result;
end function;
end procedure resetLogic; function getStatusFromRx(databus: std_logic_vector(7 downto 0)) return StatusResult is
variable result : StatusResult;
impure function statusCheck(turntaker: std_logic)return std_logic is begin
begin result.rd_sig_out := '1';
if turnTaker = '0' then -- til TX result.adresse_out := "101";
Rd_sig <= '1'; result.turn_taker_out := '0';
adresse <= "010"; return result;
turntaker <= '1';
return '1';
else -- Til RX
Rd_sig <= '1';
adresse <= "110";
turntaker <= '0';
return '0';
end if;
end function statusCheck;
impure function getStatusFromRx(databus: std_logic_vector(7 downto 0))return std_logic is
begin
Rd_sig <= '1';
adresse <= "101";
end function getStatusFromRx; end function getStatusFromRx;
impure function sendDataToTx(databus: std_logic_vector(7 downto 0)) return std_logic is impure function sendDataToTx(databus: std_logic_vector(7 downto 0)) return TxResult is
begin variable result : TxResult;
if txBusy = '0' then begin
adresse <= "001"; if txBusy = '0' then
Data_bus <= databus; result.adresse_out := "001";
Wr_sig <= '1'; result.data_bus_out := databus;
else result.wr_sig_out := '1';
Rd_sig <= '1'; result.rd_sig_out := '0';
Data_bus <= databus; else
end if; result.adresse_out := "ZZZ";
result.data_bus_out := databus;
end function sendDataToTx; result.wr_sig_out := '0';
result.rd_sig_out := '1';
end if;
return result;
end function sendDataToTx;
--Arkitekturen begynner --Arkitekturen begynner
...@@ -90,26 +107,30 @@ begin ...@@ -90,26 +107,30 @@ begin
-- prosessen begynner -- prosessen begynner
p_clk : process(all) p_clk : process(clk, rst_n)
variable internal_data : std_logic_vector(7 downto 0);
variable count : integer := 0;
variable status_result : StatusResult;
variable tx_result : TxResult;
begin begin
-- Reset er starten av oppdraget. Her sendes config-informasjon. -- Reset er starten av oppdraget. Her sendes config-informasjon.
if rst_n = '0' then if rst_n = '0' then
resetLogic; resetLogic(internal_baud, internal_parity);
internal_z(2 downto 0) <= "000"; internal_z <= "000";
count := 1; count := 1;
Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud; Data_bus <= internal_z & internal_parity & internal_baud;
Wr_sig <= '1'; Wr_sig <= '1';
adresse <= "000"; adresse <= "000";
elsif rising_edge(clk) then elsif rising_edge(clk) then
if count = "1" then if count = 1 then
internal_z(2 downto 0) <= "000"; internal_z(2 downto 0) <= "000";
Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud; Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud;
adresse <= "000"; adresse <= "000";
Wr_sig <= '1'; Wr_sig <= '1';
count := count + 1; count := count + 1;
elsif count = "2" then elsif count = 2 then
internal_z(2 downto 0) <= "110"; internal_z(2 downto 0) <= "110";
Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud; Data_bus(7 downto 0) <= internal_z & internal_parity & internal_baud;
adresse <= "110"; adresse <= "110";
...@@ -121,24 +142,36 @@ begin ...@@ -121,24 +142,36 @@ begin
Data_bus <= "ZZZZZZZZ"; Data_bus <= "ZZZZZZZZ";
end if; end if;
turnTaker <= statusChecker(turnTaker);
status_result := statusCheck(turnTaker);
Rd_sig <= status_result.rd_sig_out;
adresse <= status_result.adresse_out;
turnTaker <= status_result.turn_taker_out;
if Data_bus = "ZZZZZZZZ" then if Data_bus = "ZZZZZZZZ" then
Rd_sig <= '0'; Rd_sig <= '0';
else if Rd_sig = '1' then elsif Rd_sig = '1' then
sendDataToTx(Data_bus);
tx_result := sendDataToTx(Data_bus);
adresse <= tx_result.adresse_out;
Data_bus <= tx_result.data_bus_out;
Wr_sig <= tx_result.wr_sig_out;
Rd_sig <= tx_result.rd_sig_out;
else else
if turnTaker = '1' then -- da skal vi sjekke om TX er busy if turnTaker = '1' then -- da skal vi sjekke om TX er busy
if Data_bus(0 downto 0) = "1" then if Data_bus(0 downto 0) = "1" then
txBusy <= '1'; txBusy <= '1';
elsif turnTaker = '0' then -- Skal sjekke om Rx har data til oss, status på fifo osv. elsif turnTaker = '0' then -- Skal sjekke om Rx har data til oss, status på fifo osv.
getStatusFromRx(Data_bus); status_result := getStatusFromRx(Data_bus);
Rd_sig <= status_result.rd_sig_out;
adresse <= status_result.adresse_out;
turnTaker <= status_result.turn_taker_out;
else else
end if; end if;
end if; end if;
end if; end if;
end if; end if;
end if;
end process p_clk; end process p_clk;
......
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