fikset calculate_parity og fått TxD til å oppdatere riktig etter syklus

Tx.vhd

@@ -19,7 +19,6 @@ architecture Behavioral of Tx is
     signal baud_rate : baud_type;
 	signal baud_count : natural range 0 to 5208;
 	signal baud_clk : std_logic;
-	signal last_baud_clk : std_logic;
     -- Parity type
     type parity_type is (no_parity, even_parity, odd_parity);
     signal parity_mode : parity_type;
@@ -30,7 +29,8 @@ architecture Behavioral of Tx is
 	
 	--ovrige signaler
 	signal data_reg : std_logic_vector(7 downto 0);
-	signal bit_count : natural range 0 to 7; --er den riktig? teller det opp mellom data_reg? eller ned?
+	signal bit_count : natural range 0 to 7;
+	signal bit_to_send, ready_to_send: std_logic;
 
 	function select_baud(baud: std_logic_vector(2 downto 0)) return baud_type is
 		begin
@@ -81,24 +81,25 @@ architecture Behavioral of Tx is
 			for i in data'range loop
 				tmp := tmp xor data(i);
 			end loop;
-			return tmp xnor parity_bit;
+			return tmp xor parity_bit;
 	end function;
 
 begin
+	p_bit_send: TxD <= bit_to_send;
+
 		process(clk, rst_n) is
 			begin
 			if rst_n = '0' then
 			--resetter systemet
-			TxD <= '1';
+			--TxD <= '1';
+			bit_to_send <= '1';
 			Data_bus <= (others => 'Z');
-			last_baud_clk <= '0';
 			baud_rate <= baud_type'right;
             parity_mode <= parity_type'left;
 			tx_state <= tx_state_type'left;
 			bit_count <= 0;
 			data_reg <= (others => '0');
 			elsif rising_edge(clk) then
-				last_baud_clk <= baud_clk;
 				case adresse is
 					when "000" => -- Konfigurasjonsinnstillinger
 						if Wr_sig = '1' then
@@ -109,7 +110,7 @@ begin
 					when "001" => --Initilaiserer transmisjon
 						if tx_state = IDLE and Wr_sig = '1' then
 						data_reg <= Data_bus;
-						tx_state <= START_BIT;
+						ready_to_send <= '1';
 						else null;
 						end if;
 					when "010" =>  -- busy
@@ -125,34 +126,54 @@ begin
 					when others => null;
 				end case;
 
-				if (baud_clk = '1' and last_baud_clk = '0') then
 				case tx_state is
 					when IDLE =>
-						TxD <= '1'; --UART er høy singal når det ikke sendes noe
+						if ready_to_send = '1' then
+							tx_state <= START_BIT;
+							ready_to_send <= '0';
+						else
+							bit_to_send <= '1'; --UART er aktivt høy singal
+							tx_state <= IDLE;
+						end if;
 					when START_BIT =>
-						TxD <= '0';
-						tx_state <= DATA_BITS;
+						if baud_clk = '1' then
+							tx_state <= DATA_BITS;
+						else
+							bit_to_send <= '0';
+							tx_state <= START_BIT;
+						end if;
 					when DATA_BITS =>
-						TxD <= data_reg(bit_count);
-						if bit_count = 7 then
-							bit_count <= 0;
-							if parity_mode = no_parity then
-								tx_state <= STOP_BIT;
+						if baud_clk = '1' then
+							if bit_count = 7 then
+								bit_count <= 0;
+								if parity_mode = no_parity then
+									tx_state <= STOP_BIT;
+								else
+									tx_state <= PARITY_BIT;
+								end if;
 							else
-								tx_state <= PARITY_BIT;
+								bit_count <= bit_count + 1;
 							end if;
 						else
-							bit_count <= bit_count + 1;
+							bit_to_send <= data_reg(bit_count);
+							tx_state <= DATA_BITS;
 						end if;
 					when PARITY_BIT =>
-						TxD <= calculate_parity(data_reg, parity_mode);
-						tx_state <= STOP_BIT;
+						if baud_clk = '1' then
+							tx_state <= STOP_BIT;
+						else
+							bit_to_send <= calculate_parity(data_reg, parity_mode);
+							tx_state <= PARITY_BIT;
+						end if;
 					when STOP_BIT =>
-						TxD <= '1';
-						tx_state <= IDLE;
+					    if baud_clk = '1' then
+							tx_state <= IDLE;
+						else
+							bit_to_send <= '1';
+							tx_state <= STOP_BIT;
+						end if;
 				end case;
 			end if;
-			end if;
 		end process;
 
 		-- baud_rate Generator Process

Tx_tb.vhd

@@ -97,7 +97,7 @@ begin
 	begin
 	 Wr_sig <= '1';
 	 adresse <= "001"; -- Sender data til Tx
-	 Data_bus <= "11111111"; -- data
+	 Data_bus <= "11111101"; -- data
 	 wait for CLK_PERIOD;
 	 Wr_sig <= '0';
 	 wait for 20*CLK_PERIOD;