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Solveig Langbakk
progkrets
Commits
2364dd06
Commit
2364dd06
authored
7 months ago
by
Nils
Browse files
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Merge branch 'main' of
https://git.gvk.idi.ntnu.no/solvlang/progkrets
parents
747748b5
936d45b6
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Changes
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2 changed files
controller.vhd
+118
-49
118 additions, 49 deletions
controller.vhd
controller_tb.vhd
+3
-3
3 additions, 3 deletions
controller_tb.vhd
with
121 additions
and
52 deletions
controller.vhd
+
118
−
49
View file @
2364dd06
...
...
@@ -20,49 +20,86 @@ end Controller;
architecture
RTL
of
Controller
is
signal
internal_baud
:
std_logic_vector
(
2
downto
0
);
-- Intern
al
signal for baud
signal
internal_baud
:
std_logic_vector
(
2
downto
0
);
-- Intern
t
signal for baud
signal
internal_parity
:
std_logic_vector
(
1
downto
0
);
-- Internt signal for parity
variable
internal_data
:
std_logic_vector
(
7
downto
0
);
-- Intern databus data
variable
count
:
integer
;
signal
turnTaker
:
std_logic
;
signal
internal_z
:
std_logic_vector
(
2
downto
0
);
function
resetLogic
(
count
:
integer
)
return
integer
is
signal
txBusy
:
std_logic
;
type
StatusResult
is
record
rd_sig_out
:
std_logic
;
adresse_out
:
std_logic_vector
(
2
downto
0
);
turn_taker_out
:
std_logic
;
end
record
;
type
TxResult
is
record
adresse_out
:
std_logic_vector
(
2
downto
0
);
data_bus_out
:
std_logic_vector
(
7
downto
0
);
wr_sig_out
:
std_logic
;
rd_sig_out
:
std_logic
;
end
record
;
procedure
resetLogic
(
signal
baud_out
:
out
std_logic_vector
(
2
downto
0
);
signal
parity_out
:
out
std_logic_vector
(
1
downto
0
)
)
is
begin
case
Baud_rate_sel
is
when
"000"
=>
internal_baud
(
2
downto
0
)
<=
"000"
;
when
"001"
=>
internal_baud
(
2
downto
0
)
<=
"001"
;
when
"010"
=>
internal_baud
(
2
downto
0
)
<=
"010"
;
when
"011"
=>
internal_baud
(
2
downto
0
)
<=
"011"
;
when
"100"
=>
internal_baud
(
2
downto
0
)
<=
"100"
;
when
others
=>
internal_baud
(
2
downto
0
)
<=
"111"
;
when
"000"
=>
baud_out
<=
"000"
;
when
"001"
=>
baud_out
<=
"001"
;
when
"010"
=>
baud_out
<=
"010"
;
when
"011"
=>
baud_out
<=
"011"
;
when
"100"
=>
baud_out
<=
"100"
;
when
others
=>
baud_out
<=
"111"
;
end
case
;
case
parity_sel
is
when
"00"
=>
internal_parity
(
1
downto
0
)
<=
"00"
;
when
"01"
=>
internal_parity
(
1
downto
0
)
<=
"01"
;
when
"10"
=>
internal_parity
(
1
downto
0
)
<=
"10"
;
when
"11"
=>
internal_parity
(
1
downto
0
)
<=
"11"
;
when
others
=>
internal_parity
(
1
downto
0
)
<=
"00"
;
-- Default
when
"00"
=>
parity_out
<=
"00"
;
when
"01"
=>
parity_out
<=
"01"
;
when
"10"
=>
parity_out
<=
"10"
;
when
"11"
=>
parity_out
<=
"11"
;
when
others
=>
parity_out
<=
"00"
;
end
case
;
end
procedure
;
function
statusCheck
(
turn_taker
:
std_logic
)
return
StatusResult
is
variable
result
:
StatusResult
;
begin
if
turn_taker
=
'0'
then
result
.
rd_sig_out
:
=
'1'
;
result
.
adresse_out
:
=
"010"
;
result
.
turn_taker_out
:
=
'1'
;
else
result
.
rd_sig_out
:
=
'1'
;
result
.
adresse_out
:
=
"110"
;
result
.
turn_taker_out
:
=
'0'
;
end
if
;
return
result
;
end
function
;
end
function
resetLogic
;
function
statusCheck
(
turnTaker
:
std_logic
)
return
std_logic
is
function
getStatusFromRx
(
databus
:
std_logic_vector
(
7
downto
0
))
return
StatusResult
is
variable
result
:
StatusResult
;
begin
if
turnTaker
=
'0'
then
-- til TX
Rd_sig
<=
"1"
;
adresse
<=
"010"
;
turnTaker
<=
'1'
;
return
1
;
result
.
rd_sig_out
:
=
'1'
;
result
.
adresse_out
:
=
"101"
;
result
.
turn_taker_out
:
=
'0'
;
return
result
;
end
function
getStatusFromRx
;
impure
function
sendDataToTx
(
databus
:
std_logic_vector
(
7
downto
0
))
return
TxResult
is
variable
result
:
TxResult
;
begin
if
txBusy
=
'0'
then
result
.
adresse_out
:
=
"001"
;
result
.
data_bus_out
:
=
databus
;
result
.
wr_sig_out
:
=
'1'
;
result
.
rd_sig_out
:
=
'0'
;
else
Rd_sig
<=
"1"
;
adresse
<=
"110"
;
turnTaker
<
=
'0'
;
return
0
;
result
.
adresse_out
:
=
"ZZZ"
;
result
.
data_bus_out
:
=
databus
;
result
.
wr_sig_out
:
=
'0'
;
result
.
rd_sig_out
:
=
'1'
;
end
if
;
end
function
statusCheck
;
return
result
;
end
function
sendDataToTx
;
--Arkitekturen begynner
...
...
@@ -70,39 +107,71 @@ begin
-- prosessen begynner
p_clk
:
process
(
all
)
p_clk
:
process
(
clk
,
rst_n
)
variable
internal_data
:
std_logic_vector
(
7
downto
0
);
variable
count
:
integer
:
=
0
;
variable
status_result
:
StatusResult
;
variable
tx_result
:
TxResult
;
begin
-- Reset er starten av oppdraget. Her sendes config-informasjon.
if
rst_n
=
'0'
then
resetLogic
(
count
);
resetLogic
(
internal_baud
,
internal_parity
);
internal_z
(
2
downto
0
)
<=
"000"
;
internal_z
<=
"000"
;
count
:
=
1
;
Data_bus
(
7
downto
0
)
<=
internal_z
&
internal_parity
&
internal_baud
;
Data_bus
<=
internal_z
&
internal_parity
&
internal_baud
;
Wr_sig
<=
'1'
;
adresse
<=
"000"
;
elsif
rising_edge
(
clk
)
then
if
count
=
"1"
then
if
count
=
1
then
internal_z
(
2
downto
0
)
<=
"000"
;
Data_bus
(
7
downto
0
)
<=
internal_z
&
internal_parity
&
internal_baud
;
adresse
<=
"000"
;
Wr_sig
<=
"1"
;
Wr_sig
<=
'1'
;
count
:
=
count
+
1
;
elsif
count
=
"2"
then
elsif
count
=
2
then
internal_z
(
2
downto
0
)
<=
"110"
;
Data_bus
(
7
downto
0
)
<=
internal_z
&
internal_parity
&
internal_baud
;
adresse
<=
"110"
;
Wr_sig
<=
"1"
;
Wr_sig
<=
'1'
;
count
:
=
count
+
1
;
else
Wr_sig
<=
"0"
;
Wr_sig
<=
'0'
;
Rd_sig
<=
'0'
;
Data_bus
<=
"ZZZZZZZZ"
;
end
if
;
statusChecker
(
turnTaker
);
status_result
:
=
statusCheck
(
turnTaker
);
Rd_sig
<=
status_result
.
rd_sig_out
;
adresse
<=
status_result
.
adresse_out
;
turnTaker
<=
status_result
.
turn_taker_out
;
if
Data_bus
=
"ZZZZZZZZ"
then
Rd_sig
<=
'0'
;
elsif
Rd_sig
=
'1'
then
tx_result
:
=
sendDataToTx
(
Data_bus
);
adresse
<=
tx_result
.
adresse_out
;
Data_bus
<=
tx_result
.
data_bus_out
;
Wr_sig
<=
tx_result
.
wr_sig_out
;
Rd_sig
<=
tx_result
.
rd_sig_out
;
else
if
turnTaker
=
'1'
then
-- da skal vi sjekke om TX er busy
if
Data_bus
(
0
downto
0
)
=
"1"
then
txBusy
<=
'1'
;
elsif
turnTaker
=
'0'
then
-- Skal sjekke om Rx har data til oss, status på fifo osv.
status_result
:
=
getStatusFromRx
(
Data_bus
);
Rd_sig
<=
status_result
.
rd_sig_out
;
adresse
<=
status_result
.
adresse_out
;
turnTaker
<=
status_result
.
turn_taker_out
;
else
end
if
;
end
if
;
end
if
;
end
if
;
end
process
p_clk
;
...
...
This diff is collapsed.
Click to expand it.
controller_tb.vhd
+
3
−
3
View file @
2364dd06
...
...
@@ -21,7 +21,7 @@ architecture SimulationModel of controller_tb is
LED_msg
:
out
std_logic
;
Data_bus
:
inout
std_logic_vector
(
7
downto
0
);
parity_sel
:
in
std_logic_vector
(
1
downto
0
);
adresse
:
in
out
std_logic_vector
(
2
downto
0
);
adresse
:
out
std_logic_vector
(
2
downto
0
);
Rd_sig
,
Wr_sig
:
out
std_logic
);
end
component
;
...
...
@@ -96,7 +96,7 @@ begin
begin
msg_key
<=
'1'
;
wait
for
CLK_PERIOD
;
wait
for
CLK_PERIOD
;
--
wait for CLK_PERIOD;
msg_key
<=
'0'
;
wait
for
CLK_PERIOD
;
end
pressButton
;
...
...
@@ -105,7 +105,7 @@ begin
procedure
loopAscii
is
begin
wait
for
100
ns
;
adresse
(
2
downto
0
)
<=
"101"
;
adresse
<=
"101"
;
--wait until rising_edge(clk);
Data_bus
<=
"01000001"
;
--wait until rising_edge(clk);
...
...
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