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Tx.vhd

@@ -87,7 +87,7 @@ architecture Behavioral of Tx is
 begin
 	p_bit_send: TxD <= bit_to_send;
 
-		process(clk, rst_n) is
+	p_seq: process(clk, rst_n) is
 			begin
 			if rst_n = '0' then
 			--resetter systemet
@@ -99,7 +99,9 @@ begin
 			tx_state <= tx_state_type'left;
 			bit_count <= 0;
 			data_reg <= (others => '0');
+			ready_to_send <= '0';
 			elsif rising_edge(clk) then
+				Data_bus <= (others => 'Z');
 				case adresse is
 					when "000" => -- Konfigurasjonsinnstillinger
 						if Wr_sig = '1' then
@@ -118,8 +120,12 @@ begin
 							if tx_state = IDLE then
 								Data_bus <= (others => '0');
 							else
+								-- Sett LSB til 1 når ikke IDLE
 								Data_bus <= (others => '0');
-								Data_bus(0) <= '1'; -- Sett LSB til 1 når ikke IDLE
+								Data_bus(0) <= '1';
+								--(0 => '1', others => '0');
+								--Data_bus <= (others => '0');
+								--evt std_logic_vector(unsigned(others => '0') + 1); 
 							end if;
 						else null;
 						end if;
@@ -177,7 +183,7 @@ begin
 		end process;
 
 		-- baud_rate Generator Process
-		process(clk, rst_n)
+	p_baud_gen: process(clk, rst_n)
 		begin
 			if rst_n = '0' then
 				baud_count <= 0;

Tx_tb.vhd

@@ -17,8 +17,8 @@ architecture SimulationModel of Tx_tb is
         Port (
             clk         : in  std_logic;
             rst_n       : in  std_logic;
-	    Rd_sig      : in std_logic;
-	    Wr_sig      : in std_logic;
+	        Rd_sig      : in std_logic;
+	        Wr_sig      : in std_logic;
             adresse     : in std_logic_vector(2 downto 0);
             Data_bus    : inout std_logic_vector(7 downto 0);
             TxD         : out std_logic
@@ -90,26 +90,44 @@ begin
      Data_bus <= "00000001";  -- Sett baud rate til 57600 (001) og ingen paritet (00)
      wait for CLK_PERIOD;
 	 Wr_sig <= '0';
+     Data_bus <= (others => 'Z');
+     adresse <= (others => 'Z');
      wait for CLK_PERIOD;
 	end config;
 
+    	-- Test Case 1: Konfigurasjon av baud rate og paritet
+	procedure config2 is
+        begin
+         Wr_sig <= '1';
+         adresse <= "000";  -- Konfigurer baud rate og paritet
+         Data_bus <= "00011000";  -- Sett baud rate til 57600 (000) og ingen paritet (11)
+         wait for CLK_PERIOD;
+         Wr_sig <= '0';
+         Data_bus <= (others => 'Z');
+         adresse <= (others => 'Z');
+         wait for CLK_PERIOD;
+        end config2;
+
 	procedure send is
 	begin
 	 Wr_sig <= '1';
 	 adresse <= "001"; -- Sender data til Tx
 	 Data_bus <= "10101010"; -- data
-	 wait for CLK_PERIOD;
+	 wait for 2*CLK_PERIOD;
 	 Wr_sig <= '0';
-	 wait for 20*CLK_PERIOD;
-     wait for 0.18 ms;
+     adresse <= (others => 'Z');
+     Data_bus <= (others => 'Z');
+	 wait for CLK_PERIOD;
+     wait for 0.05 ms;
 	end send;
 
     procedure test_busy is
         begin
          Rd_sig <= '1';
-         adresse <= "010";  -- Konfigurer Ber om status
+         adresse <= "010";  -- Controller ber om status
          wait for 2*CLK_PERIOD;
          Rd_sig <= '0';
+         adresse <= (others => 'Z');
          wait for CLK_PERIOD;
          wait for 0.1 ms;
     end test_busy;
@@ -117,9 +135,16 @@ begin
 
     begin
   	tb_init;
+    wait for 0.01 ms;
 	config;
+    wait for 0.01 ms;
 	send;
     test_busy;
+    wait for 0.05 ms;
+    test_busy;
+    config2;
+    send;
+    wait for 0.1 ms;
 
 	wait for 100 ns;
 	assert false report "Testbench finished" severity failure;