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Commit 8313d379 authored by Solveig Langbakk's avatar Solveig Langbakk
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siste endringen

parent 216e909c
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...@@ -13,7 +13,7 @@ architecture SimulationModel of controller_tb is ...@@ -13,7 +13,7 @@ architecture SimulationModel of controller_tb is
-- Constant declaration -- Constant declaration
constant CLK_PERIOD : time := 20 ns; -- 50 MHz klokke constant CLK_PERIOD : time := 20 ns; -- 50 MHz klokke
-- Component declarasion -- Component declarasion hihi
component controller component controller
Port ( Port (
clk, rst_n, msg_key: in std_logic; clk, rst_n, msg_key: in std_logic;
......
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